I work for the MCP (Media & Communications
Processor) team of Nvidia. Following are the major fields of my expertise.
Memory Controller: (Sept, 2008 –till
date): For a Single Chip (Northbridge + Southbridge +iGPU) low-power solution for Penryn based platforms.
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Technology: DDR2/DDR3 SDRAM.
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Netlist only project.
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ECOs (hier &layout) for power and timing fixes/ enhancements;
Formality check and verification.
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Unit and system level directed verification: Writing directed
tests for reproducing failures seen on Silicon (in the previous chip revision) in the sims and root-causing them for ECO fix.
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Unit level randoms: Tweak/add randomization parameters to
capture/reproduce/verify failures and the fixes.
PCI Express Units:
(June-Aug, 2008):For a Southbridge(+iGPU) chipset for Havendale platform.
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Technology: PCIE Gen2.0
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System verification of PCIE based units, viz. DMI(x4), PEG(x16),
DSP-TMS(x22), PXB HUB(internal switch between USP-PEG, USP-DMI on chipset and the rest of chipset):
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Test-bench Support: These are completely newly added units
and had no testbench support. Task involved building system level API support, multi-port BFM wrappers, and multi-port APIs.
Adding System-level TB support for PCIE based units.
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Verification: Making Test-plan for the four units, writing
system-level directed tests for the features of the four units, debug and Bug tracking through bug reports.
Memory Controller: (Dec,2007 – May, 2008) : For a Single Chip (Northbridge + Southbridge + iGPU) solution for Penryn based platforms.
- Technology: DDR2/DDR3 SDRAM.
- RTL Design: Added trimmer support for Quse Fine Delay,
Advanced Path checker, modified RTL logic for RCB decoding as per low-end system memory requirements, Updated some of the
state machines accordingly.
- Test-bench support:
- System-level: Updated DIMM models and reverse RCB logic
model for new SKU; C++ based algorithms for Read/Write leveling delays; MEM-PLL and wall-clock algorithms. Updated unit and
system level monitors, and Memory Performance monitors.
- Unit-level: Modified API for unit and system level. Updated
CPU to memory Driver (BFM) and PMU BFM for memory unit verification. Added RCB test-bench for verifying the new RCB code/decode
scheme. Added tests for verifying new features.
- Verification: Test-plan; Front-end debug at unit and
system level. Functional coverage, code coverage, register coverage. Clock Domain Crossing (CDC) check.
Miscellaneous:
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Handy with computer interconnect protocols such as HT3, FSB
and CSI; Overall Computer Architecture; ATE v2 flow for DFT; Gate level simulations.
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